CMOS technology

complementary metal-oxide semiconductor (CMOS)

A complementary metal-oxide semiconductor (CMOS) is the semiconductor technology used in most of today's integrated circuits, also known as chips or microchips.

   

What is a complementary metal-oxide semiconductor (CMOS)?

A complementary metal-oxide semiconductor (CMOS) is the semiconductor technology used in most of today's integrated circuits (ICs), also known as chips or microchips. CMOS transistors are based on metal-oxide semiconductor field-effect transistor (MOSFET) technology. MOSFETs serve as switches or amplifiers that control the amount of electricity flowing between source and drain terminals, based on the amount of applied voltage.

MOSFETs use semiconductor materials to conduct electricity under certain conditions but not others. A semiconductor falls somewhere between a conductor and insulator in terms of conductivity. It typically consists of silicon and a mix of impurities that together strike the right balance of conductivity. Silicon in its pure form is not conductive.

The process of adding impurities to a material such as silicon is sometimes referred to as doping. Semiconductor doping can be applied in different degrees to control conductivity.

In MOSFETs, the impurities used for the semiconductor material depend on the semiconductor type. MOSFET semiconductors fall into one of two categories: p-type or n-type. Boron, gallium and indium are commonly used for p-type semiconductors. Phosphorus, arsenic and bismuth are commonly used for n-type semiconductors.

The p-type semiconductor, which is positively charged, carries current as electron deficiencies called holes. A hole has a positive charge that is equal to and opposite an electron charge. The electrons flow in a direction opposite the holes. The n-type semiconductor is negatively charged. In this case, the semiconductor carries current in the form of negatively charged electrons 

Evolution of CMOS Technology

Electronics and Communications is can be achieved by minimizing size of CMOS. For faster processing demands in market CMOS technologies are upgraded. Minimizing size should reduce power consumption as well as boost speed. Today Graphene is the material which is used in industries for CMOS design. IBM engineers built a very fast chip, 10000 times faster using graphene. SiC (Silicon Carbide) wafer covered with graphene for designing a high performance transistor. As computational devices becomes more and more faster, the reason behind this is innovation of new CMOS technologies. Every company cant develop most advanced technologies. Also for designing a HCMOS, the material used are III-V/Ge and Graphene. Now CMOS devices designed using Non-Planar technology replaces conventional CMOS devices with planar technology. Three-dimensional technology have tendency to reduce power consumption, size of integrated circuits and increase speed than conventional two-dimensional technology. But it is very difficult to replace the Si-CMOS with new semiconductor material based CMOS.

History &it's invention 

CMOS technology was invented in 1963 by frank wanlass while he was working at Fairchild semiconductor. CMOS is a combination of N-type and P-type MOSFET (Metal-Oxide- Semiconductor Field-Effect Transistor). CMOS technology is used for constructing integrated circuits, microprocessors, microcontrollers, sensors, RAM (Random Access Memory) and many more digital circuits. Gordons Moore observed that number of transistor doubles after every 18 months in an integrated circuit . This computerized electronics world demands more and more faster devices. This can be achievable by scaling CMOS technology from fraction of millimeters to few of nanometers in today technologies .

 From past few years Non-Planar(3D) technology by industries. This make ease towards manufacturing high speed ICs, Processors and other electronic devices. Scientist make a very sharp reduction in size of CMOS to 7nm in future CMOS technologies . Graphene is preferred to be used for future and today in 3D(three dimensional) technology. Latest material used for CMOS design is Graphene . Graphene have very attractive properties: high electron and hole mobility, planar structure, high thermal conductance, high current carrying capacity and thin body . All properties are sufficient for designing a high performance CMOS. Innovations of new technologies is very important for downsizing of CMOS integrated circuits . As scaling down of CMOS size after every decade is difficult and we have to face some problems while downscaling of CMOS exceeds certain limit.

            After bipolar junction transistor MOSFET(Metal-Oxide- Semiconductor Field Effect Transistor ) comes with very interesting feature like: low power consumption, low operating voltage, higher speed etc. which make MOSFET useful in electronics design. Two types of MOS transistor PMOS and NMOS are invented and used for designing integrated circuits. Both types have very high static power consumption. This problem is solved if and only a logic designed in such a way that it consumes no power in static state. After decades Frank Wanlass introduces a new logic designed using two complementary p-type and n-type MOSFETs.

 Two main advantages of CMOS technology is high noise immunity and very low static power consumption . The last several decades have seen innovation of new CMOS technologies with excellent features. The trends of MOS integrated circuits downsizing.

                        CMOs fabrication 

Advantages of CMOS Logic Gates

1. Extremely large fan-out capability (>50).

2. Lowest power dissipation of all gates (a few nW).

3. Very high noise-immunity and noise-margin (typically, VDD/2) 

4. Lower propagation delay than NMOS.

5. Higher speed than NMOS. Currently, computer chips operating at (or more than) 4 GHz are available in the open market.

6. Large logic swing (=VDD).

7. Only a single power supply (+ VDD) is required.

8. Directly compatible with TTL gates.

9. Temperature stability is excellent.

10. Low-voltage (1.5 V) chips are now available.

More Advantages,

• Compact (shared diffusion regions) 

• Very low static power dissipation 

• High noise margin (nearly ideal inverter voltage transfer characteristic) 

• Very well modeled and characterized 

• Mechanically robust 

• Lends itself very well to high integration levels 

• “Analog” CMOS process usually includes non-salicided poly layer for 

linear resistors. 

• SiGe BiCMOS is very useful but is a generation behind currently 

available standard CMOS

Disadvantages of CMOS Logic Gates 

1. Increased cost due to additional processing steps. But, this is being rectified.
2. Packing density less than NMOS. Using Pass-Transistor logic structure, packing density comparable to or more than that of NMOS gate is possible.
3. MOS chips must be protected from acquiring static charges by keeping the leads shorted. Static charges acquired in leads will destroy the chip. At present this problem has been rectified by using built-in protective devices or circuits.
4. The main disadvantage of the CMOS logic family is their slow speed of operation.
5. Propagation delay time for the CMOS family is found to be around 50ns whereas it is around 4 to 12 ns for the TTL logic family.